221 search results - page 31 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...
AINA
2007
IEEE
14 years 1 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Off-chip decoupling capacitor (decap) allocation is a demanding task during package and chip codesign. Existing approaches can not handle large numbers of I/O counts and large num...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...