221 search results - page 37 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...
ICDE
2006
IEEE
14 years 8 months ago
2006
IEEE
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
ERSA
2006
13 years 9 months ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
MICRO
2003
IEEE
14 years 22 days ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...