45 search results - page 6 / 9 » Reducing the Main Memory Consumptions of FPmax* and FPclose |
IEEEPACT
2007
IEEE
14 years 5 months ago
2007
IEEE
Distinguishing transient blocks from frequently used blocks enables servicing references to transient blocks from a small fully-associative auxiliary cache structure. By inserting...
DATE
2002
IEEE
14 years 3 months ago
2002
IEEE
In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and e cient architecture ...
ICNP
2003
IEEE
14 years 4 months ago
2003
IEEE
CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient...
SISW
2003
IEEE
14 years 4 months ago
2003
IEEE
— Smart cards are widely known for their tamper resistance, but only contain a small amount of memory. Though very small, this memory often contains highly valuable information (...
MICRO
2006
IEEE
14 years 4 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...