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» Reducing the Overhead of Dynamic Analysis
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TC
2008
13 years 7 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
MICRO
2008
IEEE
103views Hardware» more  MICRO 2008»
14 years 1 months ago
Testudo: Heavyweight security analysis via statistical sampling
Heavyweight security analysis systems, such as taint analysis and dynamic type checking, are powerful technologies used to detect security vulnerabilities and software bugs. Tradi...
Joseph L. Greathouse, Ilya Wagner, David A. Ramos,...
ERSHOV
2009
Springer
13 years 5 months ago
From Dynamic to Static and Back: Riding the Roller Coaster of Information-Flow Control Research
Abstract. Historically, dynamic techniques are the pioneers of the area of information flow in the 70's. In their seminal work, Denning and Denning suggest a static alternativ...
Andrei Sabelfeld, Alejandro Russo
VTC
2007
IEEE
171views Communications» more  VTC 2007»
14 years 1 months ago
Reducing Inter-Cell Handover Events based on Cell ID Information in Multi-hop Relay Systems
—To reduce handover overhead such as signaling overhead and latency, optimal handover algorithm is needed for Mobile Multi-hop Relay (MMR) systems. This article proposes a novel ...
Ji Hyun Park, Ki-Young Han, Dong-Ho Cho
ANSS
2007
IEEE
14 years 1 months ago
Performance Analysis of an Optimistic Simulator for CD++
DEVS is a formalism to describe generic dynamic systems in a hierarchical and modular way. We present new techniques for executing DEVS and CellDEVS models in parallel and distrib...
Qi Liu, Gabriel A. Wainer