201 search results - page 15 / 41 » Reducing the number of clock variables of timed automata |
AAAI
2008
13 years 10 months ago
2008
Many real-world problems are characterized by complex relational structure, which can be succinctly represented in firstorder logic. However, many relational inference algorithms ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging...
DAM
2007
13 years 7 months ago
2007
It is shown that the set of hybrid one-dimensional reversible cellular automata (CA) with the periodic boundary condition is a regular set. This has several important consequences...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...