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» Reducing the number of clock variables of timed automata
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EPEW
2006
Springer
13 years 11 months ago
A Precedence PEPA Model for Performance and Reliability Analysis
We propose new techniques to simplify the computation of the cycle times and the absorption times for a large class of PEPA models. These techniques allow us to simplify the model ...
Jean-Michel Fourneau, Leïla Kloul
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 8 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ICAPR
2001
Springer
14 years 2 days ago
A Time-Length Constrained Level Building Algorithm for Large Vocabulary Handwritten Word Recognition
In this paper we introduce a constrained Level Building Algorithm (LBA) in order to reduce the search space of a Large Vocabulary Handwritten Word Recognition (LVHWR) system. A ti...
Alessandro L. Koerich, Robert Sabourin, Ching Y. S...
ADBIS
2005
Springer
140views Database» more  ADBIS 2005»
14 years 1 months ago
D-ARIES: A Distributed Version of the ARIES Recovery Algorithm
Abstract. This paper presents an adaptation of the ARIES recovery algorithm that solves the problem of recovery in Shared Disk (SD) database systems, whilst preserving all the desi...
Jayson Speer, Markus Kirchberg
IJCAI
2003
13 years 9 months ago
Efficient Symmetry Breaking for Boolean Satisfiability
Identifying and breaking the symmetries of CNF formulae has been shown to lead to significant reductions in search times. In this paper we describe a more systematic and efficient...
Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov