201 search results - page 4 / 41 » Reducing the number of clock variables of timed automata |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the PRPG before filling the scan chain. In this paper, we present...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
FORMATS
2006
Springer
13 years 11 months ago
2006
Springer
We solve some decision problems for timed automata which were raised by S. Tripakis in [Tri04] and by E. Asarin in [Asa04]. In particular, we show that one cannot decide whether a ...
RTSS
1998
IEEE
13 years 11 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
QEST
2010
IEEE
13 years 5 months ago
2010
IEEE
We study Timed Branching Processes (TBPs), a natural extension of (multitype) Branching Processes (BPs) where each entity is equipped with a finite set of private continuous variab...