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» Reducing the number of clock variables of timed automata
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PATMOS
2004
Springer
14 years 27 days ago
Low Latency Synchronization Through Speculation
Synchronization between independently clocked regions in a high performance system is often subject to latencies of more than one clock cycle. We show how the latency can be reduce...
D. J. Kinniment, Alexandre Yakovlev
FORMATS
2005
Springer
14 years 1 months ago
On Optimal Timed Strategies
In this paper, we study timed games played on weighted timed automata. In this context, the reachability problem asks if, given a set T of locations and a cost C, Player 1 has a st...
Thomas Brihaye, Véronique Bruyère, J...
AAAI
1992
13 years 8 months ago
Inferring Finite Automata with Stochastic Output Functions and an Application to Map Learning
It is often useful for a robot to construct a spatial representation of its environment from experiments and observations, in other words, to learn a map of its environment by exp...
Thomas Dean, Dana Angluin, Kenneth Basye, Sean P. ...
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
CONCUR
2006
Springer
13 years 9 months ago
Inference of Event-Recording Automata Using Timed Decision Trees
In regular inference, the problem is to infer a regular language, typically represented by a deterministic finite automaton (DFA) from answers to a finite set of membership querie...
Olga Grinchtein, Bengt Jonsson, Paul Pettersson