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» Reducing traffic generated by conflict misses in caches
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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
14 years 4 months ago
RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache
—It is an important issue to reduce the power consumption of a hard disk that takes a large amount of computer system’s power. As a new trend, an NV cache is used to make a dis...
Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Ki...
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
13 years 11 months ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili
EUROPAR
2010
Springer
13 years 8 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
13 years 11 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
CASES
2010
ACM
13 years 5 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra