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» Reduction of Timed Hybrid Systems
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ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
15 years 9 months ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
IJAR
2008
95views more  IJAR 2008»
15 years 4 months ago
Rule reduction for efficient inferencing in similarity based reasoning
The two most important models of inferencing in approximate reasoning with fuzzy sets are Zadeh's Compositional Rule of Inference (CRI) and Similarity Based Reasoning (SBR). ...
Balasubramaniam Jayaram
GLOBECOM
2007
IEEE
15 years 10 months ago
Time-Varying Channel Complex Gains Estimation and ICI Suppression in OFDM Systems
—In this paper, we present an iterative algorithm for channel complex gains estimation with inter-sub-carrierinterference (ICI) reduction in orthogonal-frequency-divisionmultiple...
Hussein Hijazi, Laurent Ros
ISLPED
2005
ACM
109views Hardware» more  ISLPED 2005»
15 years 9 months ago
Power reduction by varying sampling rate
The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a ...
William R. Dieter, Srabosti Datta, Wong Key Kai
RTAS
2010
IEEE
15 years 1 months ago
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
Abstract--Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. Ho...
Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele