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» Reduction of Timed Hybrid Systems
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SAC
2009
ACM
15 years 11 months ago
An empirical study of incorporating cost into test suite reduction and prioritization
Software developers use testing to gain and maintain confidence in the correctness of a software system. Automated reduction and prioritization techniques attempt to decrease the...
Adam M. Smith, Gregory M. Kapfhammer
RTSS
1996
IEEE
15 years 8 months ago
Reducing the number of clock variables of timed automata
We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks wh...
Conrado Daws, Sergio Yovine
ICPR
2004
IEEE
16 years 5 months ago
Signal Discrimination Using a Support Vector Machine for Genetic Syndrome Diagnosis
In this study, a support vector machine (SVM) classifies real world data of cytogenetic signals measured from fluorescence in-situ hybridization (FISH) images in order to diagnose...
Amit David, Boaz Lerner
ICCAD
2003
IEEE
161views Hardware» more  ICCAD 2003»
16 years 1 months ago
A General S-Domain Hierarchical Network Reduction Algorithm
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
Sheldon X.-D. Tan
DAC
2006
ACM
16 years 5 months ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner