We study the model checking problem of timed automata based on SAT solving. Our work investigates alternative possibilities for coding the SAT reductions that are based on parallel...
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
This paper proposes a strategy for parallel composite event detection in Active database systems (DBS). Up to now, the detection is sequential and totally synchronized, and thus p...
Event processing systems are a promising technology for enterprise-scale applications. However, achieving scalability yet maintaining high performance is a challenging problem. Th...
Amer Farroukh, Elias Ferzli, Naweed Tajuddin, Hans...
In this work we present an Eclipse plug-in for the VInTiMe (Verifier of INtegrated TImed ModEls)1 suite of tools that combines high-level expressive power, unassisted propertypres...