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ITC
2003
IEEE

Power-aware NoC Reuse on the Testing of Core-based Systems

14 years 4 months ago
Power-aware NoC Reuse on the Testing of Core-based Systems
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider power consumption during test, while minimizing the system testing time. Experimental results with the ITC’02 SoC benchmarks show that although power constraints can preclude the full exploration of the network parallelism, this platform is still a powerful mechanism for the system test time reduction at a very low cost.
Érika F. Cota, Luigi Carro, Flávio R
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ITC
Authors Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski
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