279 search results - page 10 / 56 » Refined statistical static timing analysis through |
JPDC
2011
13 years 4 months ago
2011
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
ICCAD
2000
IEEE
14 years 1 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
DAC
2005
ACM
13 years 12 months ago
2005
ACM
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
TVLSI
2008
13 years 9 months ago
2008
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...