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ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
14 years 2 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
14 years 6 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
13 years 12 months ago
Analytical model for the impact of multiple input switching noise on timing
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraha...
ACSC
2008
IEEE
14 years 4 months ago
Product flow analysis in distribution networks with a fixed time horizon
The movement of items through a product distribution network is a complex dynamic process which depends not only on the network’s static topology but also on a knowledge of how ...
Moe Thandar Wynn, Colin J. Fidge, Arthur H. M. ter...
PEPM
2007
ACM
14 years 4 months ago
Lowering: a static optimization technique for transparent functional reactivity
Functional Reactive Programming (frp) extends traditional functional programming with dataflow evaluation, making it possible to write interactive programs in a declarative style...
Kimberley Burchett, Gregory H. Cooper, Shriram Kri...