129 search results - page 14 / 26 » Reflections on the memory wall |
WSCG
2003
13 years 8 months ago
2003
Rendering large trimmed NURBS models with high quality at interactive frame rates is of great interest for industry, since nearly all their models are designed on the basis of thi...
ICALP
2009
Springer
14 years 7 months ago
2009
Springer
We initiate the study of sublinear-time algorithms in the external memory model [14]. In this model, the data is stored in blocks of a certain size B, and the algorithm is charged...
AMKM
2003
Springer
14 years 22 days ago
2003
Springer
We first describe a multi-agent system managing a corporate memory in the form of a corporate semantic web. We then focus on a newly introduced society of agents in charge of wrap...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...