Sciweavers

91 search results - page 14 / 19
» Register Allocation for Programs in SSA-Form
Sort
View
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
13 years 11 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
CF
2009
ACM
14 years 2 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
ASPLOS
1998
ACM
13 years 11 months ago
Compiler-Controlled Memory
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
Keith D. Cooper, Timothy J. Harvey
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
14 years 1 months ago
Cooptimization of interface hardware and software for I/O controllers
The allocation of device variables on I/O registers affects the code size and performance of an I/O device driver. This work seeks the allocation with the minimal software or hard...
Kuan Jen Lin, Shih Hao Huang, Shan Chien Fang
TMC
2008
192views more  TMC 2008»
13 years 7 months ago
A Bidding Algorithm for Optimized Utility-Based Resource Allocation in Ad Hoc Networks
Abstract-- This article proposes a scheme for bandwidth allocation in wireless ad hoc networks. The quality of service (QoS) levels for each end-to-end flow are expressed using a r...
Calin Curescu, Simin Nadjm-Tehrani