39 search results - page 5 / 8 » Register File Architecture Optimization in a Coarse-Grained ... |
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
MICRO
2000
IEEE
13 years 6 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
LCTRTS
2009
Springer
14 years 1 months ago
2009
Springer
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...