39 search results - page 7 / 8 » Register File Architecture Optimization in a Coarse-Grained ... |
TVLSI
2002
13 years 7 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
USENIX
2008
13 years 10 months ago
2008
zation is a well-known method of abstracting physical resources and of separating the manipulation and use of logical resources from their underlying implementation. We have used ...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...