27 search results - page 5 / 6 » Register allocation with instruction scheduling for VLIW-arc... |
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
PLDI
2005
ACM
14 years 8 days ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
PLDI
2003
ACM
13 years 12 months ago
2003
ACM
Typed assembly languages provide a way to generate machinecheckable safety proofs for machine-language programs. But the soundness proofs of most existing typed assembly languages...
EGH
2005
Springer
14 years 7 days ago
2005
Springer
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
JUCS
2000
13 years 6 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...