Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
PDF Tools
Image Tools
Text Tools
OCR Tools
Symbol and Emoji Tools
On-screen Keyboard
Latex Math Equation to Image
Smart IPA Phonetic Keyboard
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
6
search results - page 2 / 2
»
Register binding for clock period minimization
Sort
relevance
views
votes
recent
update
View
thumb
title
160
click to vote
ASPDAC
2004
ACM
141
views
Hardware
»
more
ASPDAC 2004
»
An approach for reducing dynamic power consumption in synchronous sequential digital designs
15 years 9 months ago
Download
www.inf.ethz.ch
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf
claim paper
Read More »
« Prev
« First
page 2 / 2
Last »
Next »