1017 search results - page 150 / 204 » Register computations on ordinals |
HPCC
2009
Springer
14 years 11 days ago
2009
Springer
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
CRYPTO
2001
Springer
14 years 7 days ago
2001
Springer
Abstract. The shrinking generator is a well-known keystream generator composed of two linear feedback shift registers, LFSR1 and LFSR2, where LFSR1 is clock-controlled according to...
HPCA
2000
IEEE
14 years 4 days ago
2000
IEEE
Memorylatency isbecominganincreasingly importantperformance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we sw...
IEEEPACT
2000
IEEE
14 years 4 days ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
DAC
1999
ACM
14 years 2 days ago
1999
ACM
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...