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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
14 years 2 days ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
14 years 22 hour ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
ICCV
1998
IEEE
14 years 7 hour ago
Detecting Changes in Aerial Views of Man-Made Structures
Many applications require detecting structural changes in a scene over a period of time. Comparing intensity values of successive images is not effective as such changes don'...
Andres Huertas, Ramakant Nevatia
IPPS
1998
IEEE
14 years 1 hour ago
Partitioned Schedules for Clustered VLIW Architectures
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
Marcio Merino Fernandes, Josep Llosa, Nigel P. Top...
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
13 years 12 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...