1017 search results - page 163 / 204 » Register computations on ordinals |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
ICIAP
2005
ACM
14 years 7 months ago
2005
ACM
In this paper we describe a method for the reconstruction and visualization of functional models of monkey brains. Models are built through the registration of high resolution imag...
PERCOM
2004
ACM
14 years 7 months ago
2004
ACM
Networks of small devices, such as environmental sensors, introduce a number of new challenges for traditional protocols and approaches. In particular, the extreme resource constr...