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CF
2009
ACM
14 years 3 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
CVPR
2007
IEEE
14 years 3 months ago
Map-Enhanced UAV Image Sequence Registration and Synchronization of Multiple Image Sequences
Registering consecutive images from an airborne sensor into a mosaic is an essential tool for image analysts. Strictly local methods tend to accumulate errors, resulting in distor...
Yuping Lin, Gérard G. Medioni
IEEEPACT
2002
IEEE
14 years 2 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
MICCAI
2003
Springer
14 years 10 months ago
Vascular Atlas Formation Using a Vessel-to-Image Affine Registration Method
We have developed a method for forming vascular atlases using vascular distance maps and a novel vascular model-to-image registration method. Our atlas formation process begins wit...
Dini Chillet, Julien Jomier, Derek Cool, Stephen R...
HPCA
2008
IEEE
14 years 9 months ago
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again
Serializing instructions (SIs), such as writes to control registers, have many complex dependencies, and are difficult to execute out-of-order (OoO). To avoid unnecessary complexi...
Philip M. Wells, Gurindar S. Sohi