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CF
2004
ACM
14 years 2 months ago
Integrated temporal and spatial scheduling for extended operand clustered VLIW processors
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
Rahul Nagpal, Y. N. Srikant
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
14 years 2 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...
ICCAD
1998
IEEE
112views Hardware» more  ICCAD 1998»
14 years 1 months ago
Using precomputation in architecture and logic resynthesis
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
Soha Hassoun, Carl Ebeling
MICRO
1996
IEEE
96views Hardware» more  MICRO 1996»
14 years 1 months ago
Exceeding the Dataflow Limit via Value Prediction
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
Mikko H. Lipasti, John Paul Shen
CAL
2007
13 years 9 months ago
Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
Abstract—Some processors designed for consumer applications, such as Graphics Processing Units (GPUs) and the CELL processor, promise outstanding floating-point performance for ...
William R. Dieter, A. Kaveti, Henry G. Dietz