76 search results - page 11 / 16 » Register placement for low power clock network |
ASAP
2008
IEEE
14 years 2 months ago
2008
IEEE
NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design ...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This...
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...