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VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 9 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
IPPS
2002
IEEE
14 years 1 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
AAAI
1990
13 years 10 months ago
The Design of a Marker Passing Architecture for Knowledge Processing
Knowledge processing is very demanding on computer architectures. Knowledge processing generates subcomputation paths at an exponential rate. It is memory intensive and has high c...
Wing Lee, Dan I. Moldovan
ICRA
2006
IEEE
225views Robotics» more  ICRA 2006»
14 years 2 months ago
Constraint Optimization Coordination Architecture for Search and Rescue Robotics
— The dangerous and time sensitive nature of a disaster area makes it an ideal application for robotic exploration. Our long term goal is to enable humans, software agents, and a...
Mary Koes, Illah R. Nourbakhsh, Katia P. Sycara
ISPASS
2010
IEEE
14 years 3 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...