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ICCS
2005
Springer
14 years 29 days ago
Collecting and Exploiting Cache-Reuse Metrics
Abstract. The increasing gap of processor and main memory performance underlines the need for cache-optimizations, especially on memoryintensive applications. Tools which are able ...
Josef Weidendorfer, Carsten Trinitis
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 9 months ago
Shared reconfigurable architectures for CMPS
This paper investigates reconfigurable architectures suitable for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfi...
Matthew A. Watkins, Mark J. Cianchetti, David H. A...
CGF
1999
125views more  CGF 1999»
13 years 7 months ago
Partitioning and Handling Massive Models for Interactive Collision Detection
We describe an approach for interactive collision detection and proximity computations on massive models composed of millions of geometric primitives. We address issues related to...
Andy Wilson, Eric Larsen, Dinesh Manocha, Ming C. ...
JCNS
2010
90views more  JCNS 2010»
13 years 2 months ago
Fast Kalman filtering on quasilinear dendritic trees
Optimal filtering of noisy voltage signals on dendritic trees is a key problem in computational cellular neuroscience. However, the state variable in this problem -- the vector of...
Liam Paninski
ISCA
2005
IEEE
121views Hardware» more  ISCA 2005»
14 years 1 months ago
Direct Cache Access for High Bandwidth Network I/O
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Ram Huggahalli, Ravi R. Iyer, Scott Tetrick