Shared reconfigurable architectures for CMPS

This paper investigates reconfigurable architectures suitable for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfigurable logic can dramatically improve the performance of certain application classes, but this comes at nontrivial power and area costs. Given substantial observed time and space differences in fabric usage, we propose that pools of programmable logic should be shared among multiple cores. While a common shared pool is more compact and power efficient, fabric conflicts may lead to large performance losses relative to per-core private fabrics. We identify particular characteristics of past reconfigurable fabric designs that are particularly amenable to fabric sharing. We then propose spatially and temporally shared fabrics in a CMP. The sharing policies that we devise incur negligible performance loss compared to private fabrics, while cutting the area and peak power of the fabric by 4X.

• Type: Conference
• Year: 2008
• Where: FPL
• Authors: Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi
• Keywords: Fabric, FPL 2008, Hardware, Past Reconfigurable Fabric, Private Fabrics