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» Relative Timing Based Verification of Timed Circuits and Sys...
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121
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EOR
2010
110views more  EOR 2010»
15 years 3 months ago
Pricing surplus server capacity for mean waiting time sensitive customers
Resources including various assets of supply chains, face random demand over time and can be shared by others. We consider an operational setting where a resource is shared by two...
Sudhir K. Sinha, N. Rangaraj, N. Hemachandra
127
Voted
EMSOFT
2010
Springer
15 years 1 months ago
PinaVM: a systemC front-end based on an executable intermediate representation
SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorpo...
Kevin Marquet, Matthieu Moy
110
Voted
NN
2006
Springer
15 years 3 months ago
Speed-accuracy trade-off in planned arm movements with delayed feedback
The Vector Integration to Endpoint (VITE) circuit describes a real-time neural network model simulating behavioral and neurobiological properties of planned arm and hand movements...
Dan Beamish, I. Scott MacKenzie, Jianhong Wu
145
Voted
CASES
2007
ACM
15 years 7 months ago
SCCP/x: a compilation profile to support testing and verification of optimized code
Embedded systems are often used in safety-critical environments. Thus, thorough testing of them is mandatory. A quite active research area is the automatic test-case generation fo...
Raimund Kirner
170
Voted
CODES
2003
IEEE
15 years 9 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...