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» Reliability and Fault Tolerance in Trust
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ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
14 years 28 days ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
MIDDLEWARE
2009
Springer
14 years 3 months ago
Why Do Upgrades Fail and What Can We Do about It?
Abstract. Enterprise-system upgrades are unreliable and often produce downtime or data-loss. Errors in the upgrade procedure, such as broken dependencies, constitute the leading ca...
Tudor Dumitras, Priya Narasimhan
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 10 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
SPAA
2009
ACM
14 years 9 months ago
The weakest failure detector for wait-free dining under eventual weak exclusion
Dining philosophers is a classic scheduling problem for local mutual exclusion on arbitrary conflict graphs. We establish necessary conditions to solve wait-free dining under even...
Srikanth Sastry, Scott M. Pike, Jennifer L. Welch
DAC
2003
ACM
14 years 1 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...