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HPCA
2009
IEEE
14 years 8 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
DAC
2007
ACM
14 years 8 months ago
Design Methodology for Pipelined Heterogeneous Multiprocessor System
Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processo...
Seng Lin Shee, Sri Parameswaran
CAV
2005
Springer
173views Hardware» more  CAV 2005»
14 years 1 months ago
Building Your Own Software Model Checker Using the Bogor Extensible Model Checking Framework
Model checking has proven to be an effective technology for verification and debugging in hardware and more recently in software domains. We believe that recent trends in both th...
Matthew B. Dwyer, John Hatcliff, Matthew Hoosier, ...
ISPD
2000
ACM
113views Hardware» more  ISPD 2000»
13 years 12 months ago
Floorplan area minimization using Lagrangian relaxation
modules can be handled in constraint graphs efficiently. This Floorplan area minimization is an important problem because many modules have shape flexibilities during the floorplan...
Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. W...
ISPD
1999
ACM
85views Hardware» more  ISPD 1999»
13 years 11 months ago
Optimal partitioners and end-case placers for standard-cell layout
We study alternatives to FM-based partitioning in the context of end-case processing for top-down standard-cell placement. The primary motivation is that small partitioning instan...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...