Sciweavers

1311 search results - page 83 / 263
» Remarks on Hardware Implementation of Image Processing Algor...
Sort
View
ICIP
2005
IEEE
14 years 10 months ago
High throughput 2D DCT/IDCT processor for video coding
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron
DATE
2007
IEEE
156views Hardware» more  DATE 2007»
14 years 3 months ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
ICST
2009
IEEE
13 years 6 months ago
Proving Functional Equivalence of Two AES Implementations Using Bounded Model Checking
Bounded model checking--as well as symbolic equivalence checking--are highly successful techniques in the hardware domain. Recently, bit-vector bounded model checkers like CBMC ha...
Hendrik Post, Carsten Sinz
ICIP
2004
IEEE
14 years 10 months ago
Deringing and deblocking dct compression artifacts with efficient shifted transforms
A new method, using weighted combinations of shifted transforms, is developed for deringing and deblocking DCT compressed color images. The method shows substantial deringing impr...
Ramin Samadani, Arvind Sundararajan, Amir Said
VG
2003
13 years 10 months ago
Integrating Pre-Integration Into The Shear-Warp Algorithm
The shear-warp volume rendering algorithm is one of the fastest algorithms for volume rendering, but it achieves this rendering speed only by sacrificing interpolation between th...
Jürgen P. Schulze, Martin Kraus, Ulrich Lang,...