74 search results - page 10 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
TCAD
2002
13 years 7 months ago
2002
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
JETC
2008
13 years 5 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
SLIP
2004
ACM
14 years 23 days ago
2004
ACM
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...