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TVLSI
2008
121views more  TVLSI 2008»
15 years 3 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
108
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VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
16 years 4 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
139
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BCSHCI
2007
15 years 5 months ago
Evaluating advanced interaction techniques for navigating Google Earth
This paper presents the design and comparison of a mousebased interaction technique (hereafter IT) and two advanced IT, used in public spaces to support navigation in a 3D space. ...
Emmanuel Dubois, Philippe Truillet, Cédric ...
155
Voted
VR
2010
IEEE
198views Virtual Reality» more  VR 2010»
15 years 1 months ago
Virtual Experience Test: A virtual environment evaluation questionnaire
We present the development and evaluation of the Virtual Experience Test (VET). The VET is a survey instrument used to measure holistic virtual environment experiences based upon ...
Dustin B. Chertoff, Brian Goldiez, Joseph J. LaVio...
NOCS
2007
IEEE
15 years 10 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...