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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 11 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
ISCAS
2003
IEEE
91views Hardware» more  ISCAS 2003»
14 years 11 days ago
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity
The full-custom CMOS realization of a new modular sorting architecture is presented. The high-performance architecture is based on rank ordering, and on efficient implementation o...
Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici
FORMATS
2006
Springer
13 years 10 months ago
Adding Invariants to Event Zone Automata
Recently, a new approach to the symbolic model checking of timed automata based on a partial order semantics was introduced, which relies on event zones that use vectors of event o...
Peter Niebert, Hongyang Qu
WDAG
2004
Springer
113views Algorithms» more  WDAG 2004»
14 years 13 days ago
Bounded Version Vectors
Abstract. Version vectors play a central role in update tracking under optimistic distributed systems, allowing the detection of obsolete or inconsistent versions of replicated dat...
José Bacelar Almeida, Paulo Sérgio A...
FPL
2006
Springer
119views Hardware» more  FPL 2006»
13 years 10 months ago
The Entropy of FPGA Reconfiguration
In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propos...
Usama Malik, Oliver Diessel