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DAC
2005
ACM
13 years 10 months ago
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technolog...
Subhasish Mitra, Tanay Karnik, Norbert Seifert, Mi...
ICMCS
2010
IEEE
268views Multimedia» more  ICMCS 2010»
13 years 9 months ago
Scalable MDC for 3D Stereoscopic Video using motion vector encoding
Interest in 3D video visualization systems is a ever growing field. Such areas include the provision of 3D content to users thus opening the exploration of 3D video communication ...
Steven Adedoyin, Warnakulasuriya Anil Chandana Fer...
COMCOM
2006
93views more  COMCOM 2006»
13 years 8 months ago
On scalability properties of the Hi3 control plane
The Host Identity Indirection Infrastructure (Hi3) is a general-purpose networking architecture, derived from the Internet Indirection Infrastructure (i3) and the Host Identity Pr...
Dmitry Korzun, Andrei Gurtov
TCAD
2008
92views more  TCAD 2008»
13 years 8 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
ICASSP
2010
IEEE
13 years 6 months ago
Towards objectifying information hiding
In this paper, the concept of object-oriented embedding (OOE) is introduced into information hiding in general and particularly to steganography which is the science that involves...
Abbas Cheddad, Joan Condell, Kevin Curran, Paul Mc...