133 search results - page 3 / 27 » Resilient design in scaled CMOS for energy efficiency |
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
ARITH
2005
IEEE
14 years 1 months ago
2005
IEEE
Efficient adder design requires proper selection of a recurrence algorithm and its realization. Each of the algorithms: Weinberger’s, Ling’s and Doran’s were analyzed for it...
GLVLSI
2003
IEEE
14 years 26 days ago
2003
IEEE
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
DFT
2008
IEEE
14 years 2 months ago
2008
IEEE
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...