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ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
15 years 8 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
109
Voted
ESCIENCE
2007
IEEE
15 years 6 months ago
Fast Information Transport for an Instrument Enabled Grid
Grid-based computing frameworks leverage underutilized processing and storage resources. We present and evaluate a new high-performance, reliable middleware layer that can incorpo...
Eric Frizziero, Z. Har'El, Francesco Lelli, B. Man...
136
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PROCEDIA
2010
140views more  PROCEDIA 2010»
14 years 9 months ago
Theoretical enzyme design using the Kepler scientific workflows on the Grid
One of the greatest challenges in computational chemistry is the design of enzymes to catalyze non-natural chemical reactions. We focus on harnessing the distributed parallel comp...
Jianwu Wang, Prakashan Korambath, Seonah Kim, Scot...
134
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JSS
2006
99views more  JSS 2006»
15 years 2 months ago
A tunable hybrid memory allocator
Dynamic memory management can make up to 60% of total program execution time. Object oriented languages such as C++ can use 20 times more memory than procedural languages like C. ...
Yusuf Hasan, J. Morris Chang
IPPS
2006
IEEE
15 years 8 months ago
An evaluation of heuristics for SLA based parallel job scheduling
In the context of SLA based job scheduling for high performance grid computing, this paper investigates the behaviour of various scheduling heuristics to schedule SLA-bounded jobs...
Viktor Yarmolenko, Rizos Sakellariou