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IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 4 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
ICCAD
1998
IEEE
83views Hardware» more  ICCAD 1998»
14 years 2 months ago
Signature hiding techniques for FPGA intellectual property protection
John Lach, William H. Mangione-Smith, Miodrag Potk...
DATE
2008
IEEE
68views Hardware» more  DATE 2008»
14 years 4 months ago
Automatic Generation of Complex Properties for Hardware Designs
Property checking is a promising approach to prove the correctness of today’s complex designs. However, in practice this requires the formulation of formal properties which is a...
Frank Rogin, Thomas Klotz, Görschwin Fey, Rol...
ISSS
2000
IEEE
144views Hardware» more  ISSS 2000»
14 years 2 months ago
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
CISIS
2008
IEEE
14 years 4 months ago
Hardware Software Partitioning Problem in Embedded System Design Using Particle Swarm Optimization Algorithm
Hardware/software partitioning is a crucial problem in embedded system design. In this paper, we provide an alternative approach to solve this problem using Particle Swarm Optimiz...
Alakananda Bhattacharya, Amit Konar, Swagatam Das,...