Sciweavers

2778 search results - page 542 / 556
» Reuse Technique in Hardware Design
Sort
View
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
13 years 8 months ago
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is...
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Bab...
IOPADS
1996
100views more  IOPADS 1996»
13 years 8 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
PEPM
2009
ACM
15 years 6 months ago
Static Consistency Checking for Verilog Wire Interconnects
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
Cherif Salama, Gregory Malecha, Walid Taha, Jim Gr...
VIS
2005
IEEE
165views Visualization» more  VIS 2005»
14 years 8 months ago
High Dynamic Range Volume Visualization
High resolution volumes require high precision compositing to preserve detailed structures. This is even more desirable for volumes with high dynamic range values. After the high ...
Baoquan Chen, David H. Porter, Minh X. Nguyen, Xia...
MOBIHOC
2008
ACM
14 years 6 months ago
Improving sensor network immunity under worm attacks: a software diversity approach
Because of cost and resource constraints, sensor nodes do not have a complicated hardware architecture or operating system to protect program safety. Hence, the notorious buffer-o...
Yi Yang, Sencun Zhu, Guohong Cao