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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 3 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
INFOCOM
2007
IEEE
14 years 3 months ago
Can Retransmissions of Superexponential Documents Cause Subexponential Delays?
— Consider a generic data unit of random size L that needs to be transmitted over a channel of unit capacity. The channel dynamics is modeled as an on-off process {(Ai, Ui)}i≥1...
Predrag R. Jelenkovic, Jian Tan
LCN
2007
IEEE
14 years 3 months ago
Node Connectivity in Vehicular Ad Hoc Networks with Structured Mobility
1 Vehicular Ad hoc NETworks (VANETs) is a subclass of Mobile Ad hoc NETworks (MANETs). However, automotive ad hoc networks will behave in fundamentally different ways than the pred...
Ivan Wang Hei Ho, Kin K. Leung, John W. Polak, Rah...
ISSAC
2007
Springer
128views Mathematics» more  ISSAC 2007»
14 years 3 months ago
Productivity and performance using partitioned global address space languages
Partitioned Global Address Space (PGAS) languages combine the programming convenience of shared memory with the locality and performance control of message passing. One such langu...
Katherine A. Yelick, Dan Bonachea, Wei-Yu Chen, Ph...
LADC
2007
Springer
14 years 2 months ago
Security Patterns and Secure Systems Design
Analysis and design patterns are well established as a convenient and reusable way to build high-quality object-oriented software. Patterns combine experience and good practices t...
Eduardo B. Fernández