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FCCM
2007
IEEE
129views VLSI» more  FCCM 2007»
14 years 2 months ago
Automatic On-chip Memory Minimization for Data Reuse
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
Qiang Liu, George A. Constantinides, Konstantinos ...
IRI
2007
IEEE
14 years 2 months ago
Reuse Technique in Hardware Design
The paper presents a technique for the design of digital systems on the basis of reusable hardware templates, which are circuits with modifiable functionality that might be custom...
Valery Sklyarov, Iouliia Skliarova
ETS
2006
IEEE
113views Hardware» more  ETS 2006»
14 years 2 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
CHI
2008
ACM
14 years 8 months ago
Designing for bystanders: reflections on building a public digital forum
In this paper, we reflect on the design and deployment process of MAGICBoard, a public display deployed in a university setting that solicits the electronic votes and opinions of ...
Anthony Tang, Matthias Finke, Michael Blackstock, ...
CHI
2002
ACM
14 years 8 months ago
Introducing instant messaging and chat in the workplace
We report on our experiences of introducing an instant messaging and group chat application into geographically distributed workgroups. We describe a number of issues we encounter...
James D. Herbsleb, David L. Atkins, David G. Boyer...