: In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable a...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...