Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...
This paper presents measured probability density functions (pdfs) for the end-to-end latency of two-way remote method invocations from a CORBA client to a replicated CORBA server ...
Wenbing Zhao, Louise E. Moser, P. M. Melliar-Smith
Brokers are used in many multi-agent systems for locating agents, for routing and sharing information, for managing the system, and for legal purposes, as independent third partie...
Sanjeev Kumar, Philip R. Cohen, Hector J. Levesque
Incremental checkpointing is an cost-efficient fault tolerant technique for long running programs such as genetic algorithms. In this paper, we derive the equations for the writing...
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...