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» Reversible logic for supercomputing
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DATE
2005
IEEE
158views Hardware» more  DATE 2005»
14 years 3 months ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
MSR
2006
ACM
14 years 3 months ago
The evolution radar: visualizing integrated logical coupling information
In software evolution research logical coupling has extensively been used to recover the hidden dependencies between source code artifacts. They would otherwise go lost because of...
Marco D'Ambros, Michele Lanza, Mircea Lungu
BIRTHDAY
2000
Springer
14 years 2 months ago
Bistructures, bidomains, and linear logic
Bistructures are a generalisation of event structures which allow a representation of spaces of functions at higher types in an orderextensional setting. The partial order of caus...
Pierre-Louis Curien, Gordon D. Plotkin, Glynn Wins...
ECAI
2010
Springer
13 years 7 months ago
Complexity of Axiom Pinpointing in the DL-Lite Family of Description Logics
We investigate the complexity of axiom pinpointing for different members of the DL-Lite family of Description Logics. More precisely, we consider the problem of enumerating all mi...
Rafael Peñaloza, Baris Sertkaya
SC
2003
ACM
14 years 3 months ago
A New Parallel Kernel-Independent Fast Multipole Method
We present a new adaptive fast multipole algorithm and its parallel implementation. The algorithm is kernel-independent in the sense that the evaluation of pairwise interactions do...
Lexing Ying, George Biros, Denis Zorin, Harper Lan...