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EUROPAR
2009
Springer
14 years 3 months ago
A Multilevel Parallelization Framework for High-Order Stencil Computations
Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard ...
MTV
2006
IEEE
98views Hardware» more  MTV 2006»
14 years 2 months ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy...
SBACPAD
2003
IEEE
106views Hardware» more  SBACPAD 2003»
14 years 1 months ago
A Parallel Implementation of the LTSn Method for a Radiative Transfer Problem
— A radiative transfer solver that implements the LTSn method was optimized and parallelized using the MPI message passing communication library. Timing and profiling informatio...
Roberto P. Souto, Haroldo F. de Campos Velho, Step...
DESRIST
2009
Springer
100views Education» more  DESRIST 2009»
14 years 1 months ago
A theory-based alternative for the design of instruction: functional design
An approach to instructional design is described which avoids some of the problems traditionally associated with process design models, sometimes referred to as waterfall models. ...
Andrew S. Gibbons
ASPDAC
1998
ACM
81views Hardware» more  ASPDAC 1998»
14 years 21 days ago
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao