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» Robust system level design with analog platforms
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IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 2 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
SAC
2006
ACM
14 years 2 months ago
Hardware/software 2D-3D backprojection on a SoPC platform
The reduction of image reconstruction time is needed to spread the use of PET for research and routine clinical practice. In this purpose, this article presents a hardware/softwar...
Nicolas Gac, Stéphane Mancini, Michel Desvi...
ICMI
2005
Springer
143views Biometrics» more  ICMI 2005»
14 years 2 months ago
A look under the hood: design and development of the first SmartWeb system demonstrator
Experience shows that decisions in the early phases of the development of a multimodal system prevail throughout the life-cycle of a project. The distributed architecture and the ...
Norbert Reithinger, Simon Bergweiler, Ralf Engel, ...
DT
2006
180views more  DT 2006»
13 years 8 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...
ACSD
2010
IEEE
224views Hardware» more  ACSD 2010»
13 years 6 months ago
Robustness of Sequential Circuits
Digital components play a central role in the design of complex embedded systems. These components are interconnected with other, possibly analog, devices and the physical environm...
Laurent Doyen, Thomas A. Henzinger, Axel Legay, De...