768 search results - page 105 / 154 » Robustness of Sequential Circuits |
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
ITC
1999
IEEE
14 years 29 days ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
ICCAD
1998
IEEE
14 years 29 days ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
ICCAD
1993
IEEE
14 years 25 days ago
1993
IEEE
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
TOCL
2008
13 years 8 months ago
2008
State Machines Capture Parallel Algorithms: Correction and Extension ANDREAS BLASS University of Michigan and YURI GUREVICH Microsoft Research We consider parallel algorithms worki...